High-performance VLSI architecture of multiplierless LMS adaptive filters using distributed arithmetic

2001 ◽  
Vol 84 (5) ◽  
pp. 1-12
Author(s):  
Yoshitaka Tsunekawa ◽  
Kyo Takahashi ◽  
Shinji Toyoda ◽  
Mamoru Miura
Keyword(s):  
High Performance ◽  
Adaptive Filters ◽  
Vlsi Architecture ◽  
Distributed Arithmetic

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

Integration ◽  
2016 ◽  
Vol 54 ◽  
pp. 37-46 ◽  
Author(s):  
Basant Kumar Mohanty ◽  
Pramod Kumar Meher ◽  
Subodh Kumar Singhal ◽  
M.N.S. Swamy
Keyword(s):  
High Performance ◽  
Vlsi Architecture ◽  
Distributed Arithmetic

Energy Efficient VLSI Based DCT Architecture with Accurate Error Compensation

2014 ◽  
Vol 626 ◽  
pp. 127-135 ◽  
Author(s):  
D. Jessintha ◽  
M. Kannan ◽  
P.L. Srinivasan
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Time Complexity ◽  
High Performance ◽  
Low Power Consumption ◽  
Distributed Arithmetic ◽  
Technology Scaling ◽  
Truncation Errors ◽  
History Of ◽  
Technology Dependency

Discrete Cosine Transform (DCT) is commonly used in image compression. In the history of DCT, a milestone was the Distributed Arithmetic (DA) technique. Due to the technology dependency a multiplier-less computation was built with DA based technique. It occupied less area but the throughput is less. Later, due to the technology scaling, multiplier based architectures can be easily adapted for low-power and high-performance architecture. Fixed width multipliers [1]-[7] reduces hardware and time complexity. In this work, Radix 4 fixed width multiplier is adapted with DCT architecture due to low power consumption and saves 30% power. In order to reduce truncation errors caused during fixed width multiplication, an estimation circuit is designed based on conditional probability theory.

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

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